1. Field of the Invention
This disclosure relates to a method of fabricating a semiconductor device, and more particularly, to a method of forming self-aligned storage nodes capable of improving alignment margins with storage node contacts and of improving static capacitance.
2. Description of Related Art
As the integration density and scale-down of semiconductor memory devices increase, the size of a semiconductor memory device continues to decrease. Because of the decrease in the size of the devices, it is difficult to ensure the alignment margin between a storage node contact and a storage node during the exposure for forming the storage node of a capacitor. It is also difficult to achieve a sufficient capacitance owing to the reduction in the dimension of a unit capacitor.
FIGS. 1A through 1D are cross sectional diagrams illustrating a method of fabricating a conventional semiconductor device with a capacitor for a one-cylinder storage (OCS) structure.
Referring to FIG. 1A, a gate (not shown) is formed on a semiconductor substrate 100. A first interlayer insulating film 110 is formed on the substrate, and then etched to form self aligned contacts (SACs) 115 exposing impurity regions (not shown) of a predetermined conductivity type in the semiconductor substrate 100.
A conductive material for a contact pad, such as a polysilicon film, is deposited on the substrate comprising the SACs 115. A chemical mechanical polishing (CMP) process is then performed on the conductive material for node separation. As a result, a storage node contact pad 120 and a bitline contact pad (not shown) are formed in the SACs 115. At this time, the storage node contact pad 120 and the bitline contact pad are in electrical contact with the impurity regions (not shown) via SACs 115.
Next, a second interlayer insulating film 130, a conductive material 141 for a bit line, and a capping material 143 for a bit line such as a nitride film are sequentially deposited on the substrate, and then the conductive material 141 for a bit line and the capping material 143 for a bit line are etched to form a bit line 140 comprised of the conductive material 141 and the capping material 143. The bit line 140 is in contact with a bitline contact pad (not shown).
An insulating film for a spacer, for example, a nitride film, is deposited on the substrate and then etched back to form a spacer 145 on the side wall of the bit line 140. A third interlayer insulating film 150 is deposited on the substrate including the bit line 140 and a CMP process for planarization is performed. The third interlayer insulating film 150 is etched to form a storage node contact 155.
A conducting material for a contact plug, for example, a polysilicon film, is deposited on the substrate including the storage node contact 155 and then is etched by a CMP process and the like to form a contact plug 160. An etching stopper 170 and a sacrificial insulating film 180 are sequentially deposited on the substrate and then the sacrificial insulating film 180 is planarized by the CMP process and the like. The sacrificial insulating film 180 includes an oxide film, and the etching stopper 170 is includes a nitride film.
Referring to FIG. 1B, a photo resistive pattern 190 is formed on the sacrificial insulating film 180 in order to define an area where a storage node is to be formed in a subsequent process. The sacrificial insulating film 180 is etched using the photo resistive film pattern 190. The etching stopper 170 serves as an etching end point. The etching stopper 170 is etched to form an opening 195.
Referring to FIG. 1C, the photo resistive film pattern 190 is removed, and a conductive film for a storage node, for example, a polysilicon film 200, is deposited on the substrate including the opening 195. Referring to FIG. 1D, an undoped silicate glass (USG) (not shown) is deposited on the polysilicon film 200 and etched by an etch back or a CMP process for node isolation. Next, the USG film and the sacrificial insulating film 180 are removed to form a storage node 205 in contact with the contact plug 160.
As described above, the conventional semiconductor device fabrication method forms an opening by photo etching a sacrificial insulating film in order to form the storage node. However, it is difficult to assure the alignment margin with a storage node contact plug owing to the reduction in the size of the device and the associated process cost is expensive. It is difficult to assure the capacitance due to the reduction of the dimension of a unit capacitor.
Korean patent laid open number 2001-45911 discloses a method for fabricating a capacitor that is capable of simplifying the process and increasing the capacitance. This method does not form a contact plug that connects a storage node contact pad with a storage node, but instead forms a storage node that directly contacts the storage node contact pad.
However, this method also forms an opening by photo etching a sacrificial insulating film in order to form a storage node, therefore it is not capable of assuring an alignment margin with a storage node contact.
Embodiments of the invention address these and other limitations of the prior art.